Difference between synchronous and asynchronous D flip flop

Synchronous and Asynchronous D flip flop VHDL code is provided, their difference in code implementation and resulting waveform difference is shown. The difference between synchronous and asynchronous reset in flip flops is that in asynchronous the value stored in flip flop is outputted at the instant of reset signal application but in synchronous the value stored in flip flop is outputted only at the rising or falling edge of the clock depending upon the configuration of update of signal with clock.

The following is a VHDL code of a D type flip flop which has two architecture for synchronous and asynchronous reset.

library ieee;
use ieee.std_logic_1164.all;

entity d_ff is
port(
D : in std_logic;
Q : out std_logic;
rst : in std_logic;
clk : in std_logic
);
end d_ff;

architecture syn_rst_dff_arch of d_ff is
begin
process(clk)
begin
if clkevent and clk = 1 then
if rst = 1 then
Q <= 0;
else
Q <= D;
end if;
end if;

end process;

end syn_rst_dff_arch;

architecture asyn_rst_dff_arch of d_ff is
begin
process(clk, rst)
begin
if rst = 1 then
Q <= 0;
elsif clkevent and clk = 1 then
Q <= D;
end if;

end process;

end asyn_rst_dff_arch;


The entity part is the same, that is the ports inputs and outputs are the same. The difference is that in the asynchronous reset D flip flop, the value D is outputted to Q whenever reset signal rst is applied whereas in the synchronous D flip flop, the value D is outputted as Q in the next rising edge of the clock with reset signal applied.

The following waveform graph shows this-

In the above figure, at 10 ns, reset signal rst goes high(1), at that instant, Qsyn of synchronous D flip flop stays high but the Qasyn of asynchronous D flip flop goes immediately low. Only at 15 ns when there is rising edge of the clock does Qsyn go low. That is output of D flip flop, Q, is updated immediately in case of asynchronous but is not updated immediately in case of synchronous system.

The testbench for this simulation is below:

library ieee;
use ieee.std_logic_1164.all;

entity dff_tb is
end dff_tb;

architecture dff_tb_arch of dff_tb is

signal D : std_logic;
signal rst : std_logic;
signal clk : std_logic;
signal Qsyn : std_logic;
signal Qasyn : std_logic;

begin

DDF1 : entity work.d_ff(asyn_rst_dff_arch)
port map(D => D, Q => Qsyn, rst => rst, clk => clk);
DDF2 : entity work.d_ff(syn_rst_dff_arch)
port map(D => D, Q => Qasyn, rst => rst , clk => clk);

clk_process : process
begin
clk <= 0;
wait for 5 ns;
clk <= 1;
wait for 5 ns;
end process;

sti_process : process
begin

rst <= 0;

D <= 1;
wait for 10 ns;

rst <= 1;

D <= 1;
wait for 10 ns;

rst <= 0;
wait for 10 ns;

D <= 1;
wait for 10 ns;

wait;

end process;

end dff_tb_arch;

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