Suppose you want to design a full adder in VHDL than how will you start creating it? In this tutorial we will start from scratch to illustrate how to design a full adder from truth table to actual implementation using VHDL software.
A full adder has 3 inputs and 2 outputs. The 3 inputs are x, y which are the bits to be added and the carry input cin from previous calculation. The outputs are z which is the result of addition and cout which is the carry output.
The first step would be write down the truth table for the full adder. The truth table for the full adder is shown below.
To find the Boolean Function solution we can use Karnaugh map. There are software available which can minimize the function. One such software is the Karnaugh Map Analyzer.
Using Karnaugh Map Analyzer the solution is for Sum(S):
S = xyz+xyz+xyz+xyz
And the solution for Carry C is,
C = xz+yz
Now lets implement this circuit in VHDL using VHDL software. The vhdl code of the above Boolean equations is below:
library ieee;
use ieee.std_logic_1164.all;
entity full_adder is
port(
x,y,z : in std_logic;
s,c : out std_logic
);
end full_adder;
architecture full_adder_arch of full_adder is
begin
s <= ((x) and (not y) and (not z)) or ((not x) and (y) and (not z)) or ((not x) and (y) and (z)) or ((x) and (y) and (z));
c <= (x and (not z)) or (y and z);
end full_adder_arch;
Now the simulation waveform for input xyz=110 and xyz=111 is shown below:
The above figure shows that the circuit behaves correctly.
Next if we want to design higher order adder circuit like 4 bit adder then we can just use the above 1 bit full adder to make a 4 bit adder.
The VHDL code is shown below,
library ieee;
use ieee.std_logic_1164.all;
entity adder_ckt is
port(
a,b : in std_logic_vector(3 downto 0);
cin : in std_logic;
sum: out std_logic_vector(3 downto 0);
cout : out std_logic
);
end adder_ckt;
architecture adder_ckt of adder_ckt is
component full_adder is
port(
x,y,z : in std_logic;
s,c : out std_logic
);
end component;
signal sig1,sig2,sig3 : std_logic;
begin
adder1: full_adder port map(x => a(0), y => b(0), z => cin, s => sum(0), c => sig1);
adder2: full_adder port map(x => a(1), y => b(1), z => sig1, s => sum(1), c => sig2);
adder3: full_adder port map(x => a(2), y => b(2), z => sig2, s => sum(2), c => sig3);
adder4: full_adder port map(x => a(3), y => b(3), z => sig3, s => sum(3), c => cout);
end adder_ckt;
In the above VHDL code some notes can be taken.
First never write entity name and architecture name beginning with numeric letter(0 to 9). For example 4bit_adder for the entity name will throw error by the VHDL software like aldec. The error will say-
# Error: COMP96_0018: <name>.vhd : (5, 8): Identifier expected.
# Error: COMP96_0016: <name>.vhd : (5, 9): Design unit declaration expected.
The second thing has to do with instantiation. In the above VHDL code sig1, sig2, sig3 were declared as internal intermediate signals. We could have equally defined those required intermediate signals as:
signal sig : std_logic_vector(2 downto 0) and used sig(0), sig(1) and sig(2) instead of sig1, sig2, sig3.
The third point to hint out here is that, we could have opted not to specify the component section within the architecture. We can just remove it but then we should have rewritten the instantionatoin like the following.
adder1: entity work.full_adder port map(x => a(0), y => b(0), z => cin, s => sum(0), c => sig1);
So the summary of this tutorial is as follows.
To design adder we have to derive the truth table. That truth table must be converted to Boolean function. This Boolean function can then be implemented in VHDL using VHDL software.
Finally, we want to point out that there are many other ways to implement the adder in VHDL. Even Matlab can be used to generate the VHDL code which will be explained in the next blog post.
Meanwhile readers are encouraged to read other ways of writing adder vhdl code to gain better insights into vhdl programming.
A full adder has 3 inputs and 2 outputs. The 3 inputs are x, y which are the bits to be added and the carry input cin from previous calculation. The outputs are z which is the result of addition and cout which is the carry output.
The first step would be write down the truth table for the full adder. The truth table for the full adder is shown below.
To find the Boolean Function solution we can use Karnaugh map. There are software available which can minimize the function. One such software is the Karnaugh Map Analyzer.
Using Karnaugh Map Analyzer the solution is for Sum(S):
S = xyz+xyz+xyz+xyz
And the solution for Carry C is,
C = xz+yz
Now lets implement this circuit in VHDL using VHDL software. The vhdl code of the above Boolean equations is below:
library ieee;
use ieee.std_logic_1164.all;
entity full_adder is
port(
x,y,z : in std_logic;
s,c : out std_logic
);
end full_adder;
architecture full_adder_arch of full_adder is
begin
s <= ((x) and (not y) and (not z)) or ((not x) and (y) and (not z)) or ((not x) and (y) and (z)) or ((x) and (y) and (z));
c <= (x and (not z)) or (y and z);
end full_adder_arch;
Now the simulation waveform for input xyz=110 and xyz=111 is shown below:
The above figure shows that the circuit behaves correctly.
Next if we want to design higher order adder circuit like 4 bit adder then we can just use the above 1 bit full adder to make a 4 bit adder.
The VHDL code is shown below,
library ieee;
use ieee.std_logic_1164.all;
entity adder_ckt is
port(
a,b : in std_logic_vector(3 downto 0);
cin : in std_logic;
sum: out std_logic_vector(3 downto 0);
cout : out std_logic
);
end adder_ckt;
architecture adder_ckt of adder_ckt is
component full_adder is
port(
x,y,z : in std_logic;
s,c : out std_logic
);
end component;
signal sig1,sig2,sig3 : std_logic;
begin
adder1: full_adder port map(x => a(0), y => b(0), z => cin, s => sum(0), c => sig1);
adder2: full_adder port map(x => a(1), y => b(1), z => sig1, s => sum(1), c => sig2);
adder3: full_adder port map(x => a(2), y => b(2), z => sig2, s => sum(2), c => sig3);
adder4: full_adder port map(x => a(3), y => b(3), z => sig3, s => sum(3), c => cout);
end adder_ckt;
In the above VHDL code some notes can be taken.
First never write entity name and architecture name beginning with numeric letter(0 to 9). For example 4bit_adder for the entity name will throw error by the VHDL software like aldec. The error will say-
# Error: COMP96_0018: <name>.vhd : (5, 8): Identifier expected.
# Error: COMP96_0016: <name>.vhd : (5, 9): Design unit declaration expected.
The second thing has to do with instantiation. In the above VHDL code sig1, sig2, sig3 were declared as internal intermediate signals. We could have equally defined those required intermediate signals as:
signal sig : std_logic_vector(2 downto 0) and used sig(0), sig(1) and sig(2) instead of sig1, sig2, sig3.
The third point to hint out here is that, we could have opted not to specify the component section within the architecture. We can just remove it but then we should have rewritten the instantionatoin like the following.
adder1: entity work.full_adder port map(x => a(0), y => b(0), z => cin, s => sum(0), c => sig1);
So the summary of this tutorial is as follows.
To design adder we have to derive the truth table. That truth table must be converted to Boolean function. This Boolean function can then be implemented in VHDL using VHDL software.
Finally, we want to point out that there are many other ways to implement the adder in VHDL. Even Matlab can be used to generate the VHDL code which will be explained in the next blog post.
Meanwhile readers are encouraged to read other ways of writing adder vhdl code to gain better insights into vhdl programming.
- Full Adder design using Generate statement in VHDL and using Xilinx
- Adder design using logic gates in vhdl
- How to create adder in vhdl
- Adder Subtractor vhdl design
- Serial adder with accumulator using simulink and aldec vhdl software
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